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» Improved Table Lookup Algorithms for Postscaled Division
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TALG
2008
124views more  TALG 2008»
13 years 7 months ago
Uniform deterministic dictionaries
Abstract. We present a new analysis of the well-known family of multiplicative hash functions, and improved deterministic algorithms for selecting "good" hash functions. ...
Milan Ruzic
ICCAD
2004
IEEE
158views Hardware» more  ICCAD 2004»
14 years 4 months ago
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
Deming Chen, Jason Cong
ASPDAC
2008
ACM
108views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block sel
Content addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due t...
Jui-Yuan Hsieh, Shanq-Jang Ruan
DATE
2002
IEEE
74views Hardware» more  DATE 2002»
14 years 17 days ago
Maze Routing with Buffer Insertion under Transition Time Constraints
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao
DAC
1998
ACM
14 years 8 months ago
Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs
The logic blocks CLBs of a lookup table LUT based FPGA consist of one or more LUTs, possibly of di erent sizes. In this paper, we focus on technology mapping for CLBs with several...
Madhukar R. Korupolu, K. K. Lee, D. F. Wong