11 search results - page 2 / 3 » Improved method of cell placement with symmetry constraints ... |
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
1In this paper, we will present an effective layout method for analog circuits. We consider symmetry constraint, common centroid constraint, device merging and device clustering du...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
-- In interconnect-dominated designs, the ability to minimize layout-induced parasitic effects is crucial for rapid design closure. Deep sub-micron effects and ubiquitous interfere...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
I/O placement has always been a concern in modern IC design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
same level of system-level CAD support that is now commonplace in the IC industry.Recent advances in microfluidics are expected to lead to sensor systems for high-throughput bioche...
ICCAD
2009
IEEE
13 years 5 months ago
2009
IEEE
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...