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» Improvement of ASIC Design Processes
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ICCAD
2003
IEEE
136views Hardware» more  ICCAD 2003»
14 years 4 months ago
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
ICIP
1998
IEEE
14 years 9 months ago
Hardware Architecture for Optical Flow Estimation in Real Time
Optical flow estimation from image sequences has been for several years a mathematical process carried out by general purpose processors in no real time. In this work a specific a...
Aitzol Zuloaga, José Luis Martín, Jo...
DAC
1997
ACM
13 years 11 months ago
Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case Study
: Numerous fast algorithms for the Discrete Cosine Transform DCT have been proposed. Until recently, it has been di cult to compare di erent DCT algorithms and select one which i...
Miodrag Potkonjak, Kyosun Kim, Ramesh Karri
ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...
IPPS
2006
IEEE
14 years 1 months ago
Multi-clock pipelined design of an IEEE 802.11a physical layer transmitter
Among different wireless LAN technologies 802.11a has recently become popular due to its high throughput, large system capacity, and relatively long range. In this paper, we prop...
Maryam Mizani, Daler N. Rakhmatov