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IROS
2009
IEEE
129views Robotics» more  IROS 2009»
14 years 2 months ago
Using symmetrical regions of interest to improve visual SLAM
— Simultaneous Localization and Mapping (SLAM) based on visual information is a challenging problem. One of the main problems with visual SLAM is to find good quality landmarks,...
Gert Kootstra, Lambert Schomaker
SIGOPS
2010
179views more  SIGOPS 2010»
13 years 2 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
14 years 4 months ago
Hardware synthesis from guarded atomic actions with performance specifications
We present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. The ...
Daniel L. Rosenband
ICDE
2009
IEEE
114views Database» more  ICDE 2009»
14 years 9 months ago
On Efficient Query Processing of Stream Counts on the Cell Processor
In recent years, the sketch-based technique has been presented as an effective method for counting stream items on processors with limited storage and processing capabilities, such...
Dina Thomas, Rajesh Bordawekar, Charu C. Aggarwal,...
DAC
2003
ACM
14 years 8 months ago
A scalable software-based self-test methodology for programmable processors
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) th...
Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit D...