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» Improving Java performance using hardware translation
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109
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ICCAD
2004
IEEE
158views Hardware» more  ICCAD 2004»
15 years 11 months ago
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
Deming Chen, Jason Cong
ICCAD
2009
IEEE
117views Hardware» more  ICCAD 2009»
15 years 8 days ago
Binning optimization based on SSTA for transparently-latched circuits
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
Min Gong, Hai Zhou, Jun Tao, Xuan Zeng
SIGMETRICS
2010
ACM
201views Hardware» more  SIGMETRICS 2010»
15 years 7 months ago
Load balancing via random local search in closed and open systems
In this paper, we analyze the performance of random load resampling and migration strategies in parallel server systems. Clients initially attach to an arbitrary server, but may s...
Ayalvadi Ganesh, Sarah Lilienthal, D. Manjunath, A...
112
Voted
ISCA
2009
IEEE
137views Hardware» more  ISCA 2009»
15 years 9 months ago
A case for an interleaving constrained shared-memory multi-processor
Shared-memory multi-threaded programming is inherently more difficult than single-threaded programming. The main source of complexity is that, the threads of an application can in...
Jie Yu, Satish Narayanasamy
CF
2006
ACM
15 years 8 months ago
Dynamic thread assignment on heterogeneous multiprocessor architectures
In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distin...
Michela Becchi, Patrick Crowley