315 search results - page 6 / 63 » Improving Performance by Branch Reordering |
CASES
2007
ACM
13 years 11 months ago
2007
ACM
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
ECRTS
2005
IEEE
14 years 1 months ago
2005
IEEE
Branch prediction mechanisms are becoming commonplace within current generation processors. Dynamic branch predictors, albeit able to predict branches quite accurately in average,...
VLDB
1999
ACM
13 years 11 months ago
1999
ACM
We present a pipelining, dynamically usercontrollable reorder operator, for use in dataintensive applications. Allowing the user to reorder the data delivery on the fly increases...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal o...