A Novel Method to Improve the Test Efficiency of VLSI Tests

This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal of minimizing the test cost. Best and worst case bounds are established for the performance of a reordered sequence compared to the original sequence of test application. SEMATECH test data and simulation results are used throughout to illustrate the ideas.

• Type: Conference
• Year: 2002
• Where: VLSID
• Authors: Hailong Cui, Sharad C. Seth, Shashank K. Mehta
• Keywords: Computer Architecture, SEMATECH Test Data, Test Application, Test Cost, VLSID 2002