Sciweavers

1045 search results - page 114 / 209
» Improving SHA-2 Hardware Implementations
Sort
View
MICRO
2000
IEEE
68views Hardware» more  MICRO 2000»
14 years 2 months ago
Efficient checker processor design
The design and implementation of a modern microprocessor creates many reliability challenges. Designers must verify the correctness of large complex systems and construct implemen...
Saugata Chatterjee, Christopher T. Weaver, Todd M....
ASPDAC
1999
ACM
137views Hardware» more  ASPDAC 1999»
14 years 2 months ago
A Performance-Driven I/O Pin Routing Algorithm
This paper presents a performance-driven I/O pin routing algorithm with special consideration of wire uniformity. First, a topological routing based on min-cost max-flow algorith...
Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arun...
LCPC
1998
Springer
14 years 2 months ago
Compiling for SIMD Within a Register
Although SIMD (Single Instruction stream Multiple Data stream) parallel computers have existed for decades, it is only in the past few years that a new version of SIMD has evolved...
Randall J. Fisher, Henry G. Dietz
ICCAD
1997
IEEE
117views Hardware» more  ICCAD 1997»
14 years 2 months ago
Generalized matching from theory to application
This paper presents a novel approach for post-mapping optimization. We exploit the concept of generalized matching, a technique that nds symbolically all possible matching assignm...
Patrick Vuillod, Luca Benini, Giovanni De Micheli
ASPDAC
2007
ACM
121views Hardware» more  ASPDAC 2007»
14 years 2 months ago
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power suppl...
Sanjay Pant, David Blaauw