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ICCAD
1994
IEEE
131views Hardware» more  ICCAD 1994»
13 years 11 months ago
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
Hannah Honghua Yang, D. F. Wong
SIGMETRICS
1992
ACM
128views Hardware» more  SIGMETRICS 1992»
13 years 11 months ago
MemSpy: Analyzing Memory System Bottlenecks in Programs
To cope with the increasing difference between processor and main memory speeds, modern computer systems use deep memory hierarchies. In the presence of such hierarchies, the perf...
Margaret Martonosi, Anoop Gupta, Thomas E. Anderso...
ISARCS
2010
240views Hardware» more  ISARCS 2010»
13 years 9 months ago
Engineering a Distributed e-Voting System Architecture: Meeting Critical Requirements
Voting is a critical component of any democratic process; and electronic voting systems should be developed following best practices for critical system development. E-voting has i...
J. Paul Gibson, Eric Lallet, Jean-Luc Raffy
ASAP
2007
IEEE
112views Hardware» more  ASAP 2007»
13 years 9 months ago
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis
In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, syn...
Alain Darte, C. Quinson
VISSYM
2004
13 years 9 months ago
Occlusion Culling for Sub-Surface Models in Geo-Scientific Applications
We present a three pass occlusion culling algorithm, which makes efficient use of hardware support. Our geo-scientific sub-surface data sets consist typically of a set of high res...
John Plate, Anselm Grundhöfer, Benjamin Schmi...