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DATE
2004
IEEE
159views Hardware» more  DATE 2004»
13 years 11 months ago
Compositional Memory Systems for Data Intensive Applications
To alleviate the system performance unpredictability of multitasking applications running on multiprocessor platforms with shared memory hierarchies we propose a task level set ba...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
ISLPED
2005
ACM
102views Hardware» more  ISLPED 2005»
14 years 1 months ago
Snug set-associative caches: reducing leakage power while improving performance
As transistors keep shrinking and on-chip data caches keep growing, static power dissipation due to leakage of caches takes an increasing fraction of total power in processors. Se...
Jia-Jhe Li, Yuan-Shin Hwang
DCC
2007
IEEE
14 years 7 months ago
Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces
Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software de...
Milena Milenkovic, Aleksandar Milenkovic, Martin B...
MSO
2003
13 years 9 months ago
Simulation based Development of Efficient Hardware for Sort based Algorithms
The use of sub-optimal digital systems can at times lead to high speed, efficient, costeffective structures that are sufficient to perform needed tasks. We describe here a system ...
Niklas Hansson, Jay H. Harris
ISPASS
2010
IEEE
14 years 28 days ago
A study of hardware assisted IP over InfiniBand and its impact on enterprise data center performance
— High-performance sockets implementations such as the Sockets Direct Protocol (SDP) have traditionally showed major performance advantages compared to the TCP/IP stack over Infi...
Ryan E. Grant, Pavan Balaji, Ahmad Afsahi