7 search results - page 1 / 2 » Improving validation coverage metrics to account for limited... |
ASPDAC
2012
ACM
12 years 6 months ago
2012
ACM
—In both pre-silicon and post-silicon validation, the detection of design errors requires both stimulus capable of activating the errors and checkers capable of detecting the beh...
ICCD
2001
IEEE
14 years 7 months ago
2001
IEEE
We present a simulation-based semi-formal verification method for sequential circuits described at the registertransfer level. The method consists of an iterative loop where cove...
ICCAD
1996
IEEE
14 years 3 months ago
1996
IEEE
Functional simulation is the most widely used method for design verification. At various levels of abstraction, e.g., behavioral, register-transfer level and gate level, the design...
GECCO
2005
Springer
14 years 4 months ago
2005
Springer
In this study, we introduce two improved assessment metrics of multiobjective optimizers, Nondominated Ratio and Spacing Distribution, and analyze their rationality and validity. ...
ICCAD
2010
IEEE
13 years 8 months ago
2010
IEEE
Trace buffer technology allows tracking the values of a few number of state elements inside a chip within a desired time window, which is used to analyze logic errors during post-s...