309 search results - page 29 / 62 » In-Network Cache Coherence |
SIGGRAPH
1996
ACM
13 years 11 months ago
1996
ACM
We present a new method that utilizes path coherence to accelerate walkthroughs of geometrically complex static scenes. As a preprocessing step, our method constructs a BSP-tree t...
ISCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Historically, processor accesses to memory-mapped device registers have been marked uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence, ...
ISCA
2003
IEEE
14 years 28 days ago
2003
IEEE
Many future shared-memory multiprocessor servers will both target commercial workloads and use highly-integrated “glueless” designs. Implementing low-latency cache coherence i...
CC
2008
Springer
13 years 9 months ago
2008
Springer
Heterogeneous multi-core and streaming architectures such as the GPU, Cell, ClearSpeed, and Imagine processors have better power/ performance ratios and memory bandwidth than tradi...
HPCA
2007
IEEE
14 years 8 months ago
2007
IEEE
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...