46 search results - page 3 / 10 » Incremental Diagnosis and Correction of Multiple Faults and ... |
DFT
2003
IEEE
14 years 27 days ago
2003
IEEE
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
GLVLSI
2008
IEEE
13 years 7 months ago
2008
IEEE
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...
GLVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
We develop a novel on-line built-in self-test (BIST) technique for testing FPGAs that has a very high diagnosability even in presence of clustered faults, a fault pattern for whic...
ATS
2002
IEEE
14 years 17 days ago
2002
IEEE
We propose an effective approach to diagnose multiple design errors in HDL designs with only one erroneous test case. Error candidates will be greatly reduced while ensuring that ...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
To reduce test data volumes, encoded tests and compacted test responses are widely used in industry. Use of test response compaction negatively impacts fault diagnosis since the e...