42 search results - page 7 / 9 » Inductive interconnect width optimization for low power |
ICS
2005
Tsinghua U.
14 years 26 days ago
2005
Tsinghua U.
BlueGene/L is currently the world’s fastest supercomputer. It consists of a large number of low power dual-processor compute nodes interconnected by high speed torus and collect...
FPGA
2003
ACM
14 years 17 days ago
2003
ACM
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contri...
ISCA
2008
IEEE
13 years 7 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
ICCD
2008
IEEE
14 years 4 months ago
2008
IEEE
Abstract— Over the last decade, the design of ultra-lowpower digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contri...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Computer systems have become powerful enough to process continuous data streams such as video or animated graphics. While processing power and communication bandwidth of today...