174 search results - page 24 / 35 » Instruction Fetch Mechanisms for Multipath Execution Process... |
ASPLOS
2006
ACM
13 years 11 months ago
2006
ACM
Transient faults are expected a be a major design consideration in future microprocessors. Recent proposals for transient fault detection in processor cores have revolved around t...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although spe...
ISCA
1999
IEEE
13 years 11 months ago
1999
IEEE
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...
MICRO
2000
IEEE
13 years 11 months ago
2000
IEEE
Register integration (or simply integration) is a mechanism for incorporating speculative results directly into a sequential execution using data-dependence relationships. In this...
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
Long-latency loads are critical in today's processors due to the ever-increasing speed gap with memory. Not only do these loads block the execution of dependent instructions,...