174 search results - page 34 / 35 » Instruction Fetch Mechanisms for Multipath Execution Process... |
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
CF
2006
ACM
14 years 1 months ago
2006
ACM
In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distin...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Modern processors can issue and execute multiple instructions per cycle, often performing multiple memory operations simultaneously. To reduce stalls due to resource conflicts, m...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
High-performance multiprocessor systems built around out-of-order processors with aggressive branch predictors execute many memory references that turn out to be on a mispredicted...
ISLPED
2004
ACM
14 years 27 days ago
2004
ACM
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...