1192 search results - page 6 / 239 » Instruction Level Distributed Processing |
MICRO
2003
IEEE
13 years 12 months ago
2003
IEEE
Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically req...
MICRO
1992
IEEE
13 years 10 months ago
1992
IEEE
This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC arch...
DATE
2006
IEEE
14 years 23 days ago
2006
IEEE
This paper presents an Application Specific Instruction Set Processor (ASIP) design for the implementation of a class of nonlinear image processing algorithms, the Retinex-like fi...
DAC
2003
ACM
13 years 12 months ago
2003
ACM
Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and timeto-ma...
MICRO
1995
IEEE
13 years 10 months ago
1995
IEEE
Accurate instruction fetch and branch prediction is increasingly important on today’s wide-issue architectures. Fetch prediction is the process of determining the next instructi...