2784 search results - page 107 / 557 » Instruction Level Parallelism |
127
Voted
HPCA
2006
IEEE
15 years 8 months ago
2006
IEEE
Performance of multithreaded programs is heavily influenced by the latencies of the thread management and synchronization operations. Improving these latencies becomes especially...
116
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HPCA
2004
IEEE
16 years 3 months ago
2004
IEEE
Modern out-of-order processors tolerate long latency memory operations by supporting a large number of inflight instructions. This is particularly useful in numerical applications...
122
Voted
IFIP
2010
Springer
14 years 9 months ago
2010
Springer
Abstract. In this article, we present a flexible simulation environment for embedded real-time software refinement by a mixed level cosimulation. For this, ne the native speed of a...
147
Voted
DATE
2008
IEEE
15 years 9 months ago
2008
IEEE
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
105
Voted
ISCA
1998
IEEE
15 years 6 months ago
1998
IEEE
Accurate branch prediction is essential for obtaining high performance in pipelined superscalar processors that execute instructions speculatively. Some of the best current predic...