2784 search results - page 91 / 557 » Instruction Level Parallelism |
124
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HPCN
1998
Springer
15 years 6 months ago
1998
Springer
This paper presents a new architecture organisation, the dynamically trace scheduled VLIW (DTSVLIW), that can be used to implement machines that execute the code of current RISC o...
103
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HPCA
2006
IEEE
16 years 2 months ago
2006
IEEE
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
128
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HPCA
2005
IEEE
16 years 2 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
124
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ICS
2005
Tsinghua U.
15 years 8 months ago
2005
Tsinghua U.
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
90
Voted
HPCA
2007
IEEE
16 years 2 months ago
2007
IEEE