113 search results - page 3 / 23 » Instruction Scheduling Based on Subgraph Isomorphism for a H... |
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
ISVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
Intelligent mobile information devices require lowpower and high-performance processors. In order to reduce energy consumption with maintaining computing performance, we proposed ...
CCGRID
2010
IEEE
13 years 6 months ago
2010
IEEE
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...
HPCA
2007
IEEE
14 years 7 months ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction sc...