113 search results - page 3 / 23 » Instruction Scheduling Based on Subgraph Isomorphism for a H... |
119
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HPCA
2006
IEEE
16 years 3 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
153
Voted
ISVLSI
2008
IEEE
15 years 9 months ago
2008
IEEE
Intelligent mobile information devices require lowpower and high-performance processors. In order to reduce energy consumption with maintaining computing performance, we proposed ...
119
Voted
CCGRID
2010
IEEE
15 years 2 months ago
2010
IEEE
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...
124
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HPCA
2007
IEEE
16 years 3 months ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
123
Voted
ICCD
2006
IEEE
16 years 8 days ago
2006
IEEE
This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction sc...