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» Instruction Set Limitation in Support of Software Diversity
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ISCA
2006
IEEE
125views Hardware» more  ISCA 2006»
14 years 1 months ago
Architectural Semantics for Practical Transactional Memory
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
Austen McDonald, JaeWoong Chung, Brian D. Carlstro...
LCTRTS
2004
Springer
14 years 1 months ago
Feedback driven instruction-set extension
Application specific instruction-set processors combine an efficient general purpose core with special purpose functionality that is tailored to a particular application domain. ...
Uwe Kastens, Dinh Khoi Le, Adrian Slowik, Michael ...
ICITA
2005
IEEE
14 years 1 months ago
DREAM: A Practical Product Line Engineering Using Model Driven Architecture
Both product line engineering (PLE) and model driven architecture (MDA) are emerging as effective paradigms for building a family of applications in cost effective way. PLE suppor...
Soo Dong Kim, Hyun Gi Min, Jin Sun Her, Soo Ho Cha...
CODES
2005
IEEE
14 years 1 months ago
Improving superword level parallelism support in modern compilers
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...
Christian Tenllado, Luis Piñuel, Manuel Pri...
CASES
2007
ACM
13 years 11 months ago
Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms
Many MPSoC applications are loop-intensive and amenable to automatic parallelization with suitable compiler support. One of the key components of any compiler-parallelized code is...
Andrea Marongiu, Luca Benini, Mahmut T. Kandemir