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» Instruction level power model of microcontrollers
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ISSS
2000
IEEE
91views Hardware» more  ISSS 2000»
13 years 12 months ago
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
Tony Givargis, Frank Vahid, Jörg Henkel
ECRTS
2008
IEEE
14 years 1 months ago
Temporal Analysis for Adapting Concurrent Applications to Embedded Systems
Embedded services and applications that interact with the real world often, over time, need to run on different kinds of hardware (low-cost microcontrollers to powerful multicore ...
Sibin Mohan, Johannes Helander
DAC
2002
ACM
14 years 8 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
WSC
2007
13 years 9 months ago
High-performance computing enables simulations to transform education
This paper presents the case that education in the 21st Century can only measure up to national needs if technologies developed in the simulation community, further enhanced by th...
Dan M. Davis, Thomas D. Gottschalk, Laurel K. Davi...
ISLPED
2005
ACM
87views Hardware» more  ISLPED 2005»
14 years 1 months ago
Runtime identification of microprocessor energy saving opportunities
High power consumption and low energy efficiency have become significant impediments to future performance improvements in modern microprocessors. This paper contributes to the so...
W. L. Bircher, M. Valluri, J. Law, L. K. John