369 search results - page 3 / 74 » Instruction set mapping for performance optimization |
ASPDAC
2004
ACM
14 years 15 days ago
2004
ACM
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
IROS
2009
IEEE
14 years 1 months ago
2009
IEEE
Abstract— Robotics researchers are often faced with realtime constraints, and for that reason algorithmic and implementation-level optimization can dramatically increase the over...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
Industry’s demand for flexible embedded solutions providing high performance and short time-to-market has led to the development of configurable and extensible processors. The...
ISCA
2005
IEEE
14 years 20 days ago
2005
IEEE
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized ins...