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FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
14 years 1 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
CP
2007
Springer
14 years 1 months ago
Scheduling Conditional Task Graphs
The increasing levels of system integration in Multi-Processor System-on-Chips (MPSoCs) emphasize the need for new design flows for efficient mapping of multi-task applications o...
Michele Lombardi, Michela Milano
IEEEARES
2008
IEEE
14 years 2 months ago
Reliability Analysis using Graphical Duration Models
Reliability analysis has become an integral part of system design and operating. This is especially true for systems performing critical tasks such as mass transportation systems....
Roland Donat, Laurent Bouillaut, Patrice Aknin, Ph...
DSD
2006
IEEE
95views Hardware» more  DSD 2006»
13 years 11 months ago
Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication
We present a performance-oriented refinement approach that refines a perfectly synchronous communication model onto Network-on-Chip (NoC) communication. We first identify four bas...
Zhonghai Lu, Ingo Sander, Axel Jantsch
ICCAD
2003
IEEE
145views Hardware» more  ICCAD 2003»
14 years 4 months ago
Manufacturing-Aware Physical Design
Ultra-deep submicron manufacturability impacts physical design (PD) through complex layout rules and large guardbands for process variability; this creates new requirements for ne...
Puneet Gupta, Andrew B. Kahng