27 search results - page 3 / 6 » Integrated placement and skew optimization for rotary clocki... |
DAC
2009
ACM
14 years 5 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
ISPD
2007
ACM
14 years 12 days ago
2007
ACM
The existing temperature-aware clock embedding assumes a time-invariant temperature gradient. However, it is not solved how to find the worst-case temperature gradient leading to...
DAC
2008
ACM
14 years 19 days ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
GLVLSI
2009
IEEE
14 years 5 months ago
2009
IEEE
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
ISQED
2002
IEEE
14 years 3 months ago
2002
IEEE
All synchronous CMOS integrated systems have to pay some sequencing overhead. This overhead includes the skew and the jitter of the clock. It also includes the setup time and the ...