42 search results - page 4 / 9 » Interconnect Delay Estimation Models for Synthesis and Desig... |
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
In this paper, we study the full-chp interconnect power modeling. ,We show that repeater,insertion is no longer sufficient to achievethe targetfrequencies specifiedhy ITRS, and de...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
Rapid approximation of the transient response of high-speed global interconnects is needed to estimate the time delay, crosstalk, and overshoot in a GSI multilevel wiring network....
DATE
2003
IEEE
14 years 19 days ago
2003
IEEE
In today’s deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field prog...
VLSID
2005
IEEE
14 years 7 months ago
2005
IEEE
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...