42 search results - page 7 / 9 » Interconnect Delay Estimation Models for Synthesis and Desig... |
DATE
2002
IEEE
14 years 9 days ago
2002
IEEE
Advancing technology drives design technology and thus design automation EDA . How to model interconnect, how to handle degradation of signal integrity and increasing power densi...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local ...
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...
BXML
2004
13 years 8 months ago
2004
: ExtraPlanT system is a multi-agent production planning system designed for small factories, which needs to react quickly on market changes. To deal with this requirement, ExtraPl...
ISSS
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...