27 search results - page 5 / 6 » Interconnect capacitance estimation for FPGAs |
FPL
2007
Springer
14 years 1 months ago
2007
Springer
This paper introduces a software supported methodology for exploring/evaluating 3D FPGA architectures. Two new CAD tools are developed: (i) the 3DPRO for placement and routing on ...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Dynamic address compression schemes that exploit address locality can help reduce both address bus energy and cost simultaneously with only a small performance penalty. In this wo...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local ...
IPPS
2002
IEEE
14 years 15 days ago
2002
IEEE
Accurate estimation of signal delay is critical to the design and verification of VLSI circuits. At very high frequencies, signal delay in circuits with small feature sizes is do...
IPPS
2003
IEEE
14 years 25 days ago
2003
IEEE
Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of tra...