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» Interconnect capacitance extraction for system LCD circuits
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GLVLSI
2008
IEEE
129views VLSI» more  GLVLSI 2008»
14 years 2 months ago
Variational capacitance modeling using orthogonal polynomial method
In this paper, we propose a novel statistical capacitance extraction method for interconnects considering process variations. The new method, called statCap, is based on the spect...
Jian Cui, Gengsheng Chen, Ruijing Shen, Sheldon X....
DATE
2003
IEEE
120views Hardware» more  DATE 2003»
14 years 29 days ago
Crosstalk Reduction in Area Routing
Interconnect delay dominates system delay in modern circuits, and with reduced feature sizes, coupling capacitance and signal crosstalk have become significant issues. By spacing...
Ryon M. Smey, Bill Swartz, Patrick H. Madden
ICCD
2005
IEEE
221views Hardware» more  ICCD 2005»
14 years 4 months ago
Broadband Impedance Matching for Inductive Interconnect in VLSI Packages
Abstract— Noise induced by impedance discontinuities from VLSI packaging is one of the leading challenges facing system level designers in the next decade. The performance of IC ...
Brock J. LaMeres, Sunil P. Khatri
GLVLSI
2009
IEEE
262views VLSI» more  GLVLSI 2009»
13 years 5 months ago
Power distribution paths in 3-D ICS
Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (...
Vasilis F. Pavlidis, Giovanni De Micheli
3DIC
2009
IEEE
279views Hardware» more  3DIC 2009»
14 years 2 months ago
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...