816 search results - page 78 / 164 » Interconnect design methods for memory design |
120
Voted
ISCAS
2007
IEEE
15 years 10 months ago
2007
IEEE
—A shared bus is a suitable structure for minimizing the interconnections costs in system synthesis. It has also been shown that the word-length of Functional Units has a great i...
118
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DATE
2005
IEEE
15 years 9 months ago
2005
IEEE
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
142
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CODES
2008
IEEE
15 years 10 months ago
2008
IEEE
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
136
Voted
MICRO
2010
IEEE
15 years 1 months ago
2010
IEEE
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
147
Voted
HPCA
2011
IEEE
14 years 7 months ago
2011
IEEE
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...