731 search results - page 16 / 147 » Interconnect modeling for improved system-level design optim... |
GLVLSI
2003
IEEE
14 years 25 days ago
2003
IEEE
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
DAC
1999
ACM
13 years 12 months ago
1999
ACM
Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these m...
ISPD
2005
ACM
14 years 1 months ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
WSC
2008
13 years 10 months ago
2008
This research presents optimized maintenance design using simulation to analyze the capability of auto part manufacturing production system. The integration of simulation and opti...