731 search results - page 61 / 147 » Interconnect modeling for improved system-level design optim... |
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
ISPD
2010
ACM
14 years 2 months ago
2010
ACM
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
TASE
2008
IEEE
13 years 7 months ago
2008
IEEE
Abstract--Cluster tools are widely used as semiconductor manufacturing equipment. While throughput analysis and scheduling of single-cluster tools have been well-studied, research ...
CF
2010
ACM
14 years 23 days ago
2010
ACM
Over the past decade, the trajectory to the petascale has been built on increased complexity and scale of the underlying parallel architectures. Meanwhile, software developers hav...
IPCCC
2007
IEEE
14 years 2 months ago
2007
IEEE
Rapidly-spreading malicious software is an important threat on today’s computer networks. Most solutions that have been proposed to counter this threat are based on our ability ...