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ERSA
2010
172views Hardware» more  ERSA 2010»
13 years 5 months ago
A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
Heiner Giefers, Marco Platzner
DAC
2006
ACM
14 years 8 months ago
Are carbon nanotubes the future of VLSI interconnections?
Increasing resistivity of copper with scaling and rising demands on current density requirements are driving the need to identify new wiring solutions for deep nanometer scale VLS...
Kaustav Banerjee, Navin Srivastava
DSN
2008
IEEE
14 years 1 months ago
A fault-tolerant directory-based cache coherence protocol for CMP architectures
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
Ricardo Fernández Pascual, José M. G...
DAC
1996
ACM
13 years 11 months ago
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
Christian Legl, Bernd Wurth, Klaus Eckl
DSN
2006
IEEE
14 years 1 months ago
Exploring Fault-Tolerant Network-on-Chip Architectures
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are ...
Dongkook Park, Chrysostomos Nicopoulos, Jongman Ki...