The GasP family of asynchronous circuits provides controls for simple pipelines, for branching and joining pipelines, for round-robin scatter and gather, for datadependent scatter...
This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power suppl...
—A low-latency, HDL-synthesizable dynamic clock frequency controller is presented as a time-efficient alternative to full-custom implementations. Frequency division of a fully in...
Robert M. Senger, Eric D. Marsman, Gordy A. Carich...
This paper describes a solution for the generation of true random numbers in a purely digital fashion; making it suitable for any FPGA type, because no FPGA vendor specific featur...
Dries Schellekens, Bart Preneel, Ingrid Verbauwhed...
This paper presents a framework for CMOS ring oscillator phase noise analysis for given power consumption specifications. This model considers both linear and nonlinear operation...