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» Latch Modeling for Statistical Timing Analysis
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DAC
2003
ACM
14 years 9 months ago
Temporofunctional crosstalk noise analysis
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal tra...
Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H...
DAC
2004
ACM
13 years 11 months ago
Statistical gate delay model considering multiple input switching
There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assum...
Aseem Agarwal, Florentin Dartu, David Blaauw
DATE
2003
IEEE
120views Hardware» more  DATE 2003»
14 years 1 months ago
Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step
Abstract — This paper defines a new diagnosis problem for diagnosing delay defects based upon statistical timing models. We illustrate the differences between the delay defect d...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-...
CVPR
2000
IEEE
14 years 10 months ago
Statistical Modeling and Performance Characterization of a Real-Time Dual Camera Surveillance System
The engineering of computer vision systems that meet application speci c computational and accuracy requirements is crucial to the deployment of real-life computer vision systems....
Michael Greiffenhagen, Visvanathan Ramesh, Dorin C...
ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
14 years 4 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou