The number of cores present on-chip is increasing rapidly. The on-chip network that connects these cores needs to scale efficiently. The topology of on-chip networks is an importan...
Conventional wireless networks employ a contention based channel access mechanism, which not only imposes high latency but also reduces goodput of the network. Lack of interference...
Dola Saha, Aveek Dutta, Dirk Grunwald, Douglas C. ...
Conventional packet-switched on-chip routers provide good resource sharing while minimizing latencies through various techniques. A virtual channel (VC) is allocated on a per-pack...
— Grido is an architecture that targets a network operator intending to provide enhanced services to its customers. This is achieved by setting up a “backbone” overlay networ...
Shirshanka Das, Alok Nandan, Michael G. Parker, Gi...
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...