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» Layout synthesis for datapath designs
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DAC
2004
ACM
14 years 9 months ago
ORACLE: optimization with recourse of analog circuits including layout extraction
Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens...
Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd
ISSS
2002
IEEE
176views Hardware» more  ISSS 2002»
14 years 1 months ago
Controller Estimation for FPGA Target Architectures during High-Level Synthesis
In existing synthesis systems, the influence of the area and delay of the controller is not or not sufficiently taken into account. But the controller can have a big influence,...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
ISPD
2012
ACM
252views Hardware» more  ISPD 2012»
12 years 4 months ago
Towards layout-friendly high-level synthesis
There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis ha...
Jason Cong, Bin Liu 0006, Guojie Luo, Raghu Prabha...
GCB
2006
Springer
158views Biometrics» more  GCB 2006»
14 years 7 days ago
Microarray Layout as Quadratic Assignment Problem
Abstract: The production of commercial DNA microarrays is based on a light-directed chemical synthesis driven by a set of masks or micromirror arrays. Because of the natural proper...
Sérgio A. de Carvalho, Sven Rahmann
DAC
1999
ACM
14 years 9 months ago
Subwavelength Lithography and Its Potential Impact on Design and EDA
This tutorial paper surveys the potential implications of subwavelength optical lithography for new tools and flows in the interface between layout design and manufacturability. W...
Andrew B. Kahng, Y. C. Pati