129 search results - page 13 / 26 » Layout synthesis for datapath designs |
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
Abstract—Reducing resource usage is one of the most important optimization objectives in behavioral synthesis due to its direct impact on power, performance and cost. The datapat...
ISSS
1995
IEEE
14 years 4 days ago
1995
IEEE
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
ASPDAC
1999
ACM
14 years 27 days ago
1999
ACM
Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing CMP which has varying e ects on device and interconnect features, depending on loca...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard ...
AHS
2007
IEEE
14 years 18 days ago
2007
IEEE
In this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. The inputs of...