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» Leakage Current Reduction in Data Caches on Embedded Systems
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CF
2005
ACM
13 years 11 months ago
Drowsy region-based caches: minimizing both dynamic and static power dissipation
Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal...
Michael J. Geiger, Sally A. McKee, Gary S. Tyson
ICCD
2006
IEEE
189views Hardware» more  ICCD 2006»
14 years 6 months ago
A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems
— Traditional level-one instruction caches and data caches for embedded systems typically have the same capacities. Configurable caches either shut down a part of the cache to su...
Chuanjun Zhang
ICCD
2001
IEEE
84views Hardware» more  ICCD 2001»
14 years 6 months ago
Static Energy Reduction Techniques for Microprocessor Caches
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of increased static energy consumption ...
Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, S...
CF
2005
ACM
13 years 11 months ago
Exploiting temporal locality in drowsy cache policies
Technology projections indicate that static power will become a major concern in future generations of high-performance microprocessors. Caches represent a significant percentage ...
Salvador Petit, Julio Sahuquillo, Jose M. Such, Da...
DAC
2008
ACM
14 years 10 months ago
Miss reduction in embedded processors through dynamic, power-friendly cache design
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
Garo Bournoutian, Alex Orailoglu