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» Leakage Current Reduction in VLSI Systems
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SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
14 years 1 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann
DATE
2002
IEEE
156views Hardware» more  DATE 2002»
14 years 17 days ago
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction
We present a Dynamic VTH Scaling (DVTS) scheme to save the leakage power during active mode of the circuit. The power saving strategy of DVTS is similar to that of the Dynamic VDD...
Chris H. Kim, Kaushik Roy
VLSID
2002
IEEE
107views VLSI» more  VLSID 2002»
14 years 8 months ago
Estimation of Maximum Power-Up Current
Power gating is emerging as a viable solution to reduction of leakage current. However, power gated circuits are different from the conventional designs in the sense that a power-...
Fei Li, Lei He, Kewal K. Saluja
DATE
2006
IEEE
142views Hardware» more  DATE 2006»
14 years 1 months ago
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
Saraju P. Mohanty, Ramakrishna Velagapudi, Elias K...
VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
14 years 8 months ago
Statistical Leakage and Timing Optimization for Submicron Process Variation
Leakage power is becoming a dominant contributor to the total power consumption and dual-Vth assignment is an efficient technique to decrease leakage power, for which effective de...
Yuanlin Lu, Vishwani D. Agrawal