6 search results - page 1 / 2 » Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox... |
TVLSI
2008
13 years 7 months ago
2008
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
SOCC
2008
IEEE
14 years 1 months ago
2008
IEEE
First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With s...
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract— We study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above wh...