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PCRCW
1997
Springer
14 years 4 days ago
Power/Performance Trade-offs for Direct Networks
High performance portable and space-borne systems continue to demand increasing computation speeds while concurrently attempting to satisfy size, weight, and power constraints. As...
Chirag S. Patel, Sek M. Chai, Sudhakar Yalamanchil...
ISCAS
2006
IEEE
110views Hardware» more  ISCAS 2006»
14 years 2 months ago
Network-on-chip link analysis under power and performance constraints
— This paper analyzes the behavior of interconnects in the highly structured environment of a network-on-chip (NoC). Two distinct classes of wires are considered, namely links be...
Manho Kim, Daewook Kim, Gerald E. Sobelman
DATE
2009
IEEE
147views Hardware» more  DATE 2009»
14 years 2 months ago
Decoupling capacitor planning with analytical delay model on RLC power grid
— Decoupling capacitors (decaps) are typically used to reduce the noise in the power supply network. Because the delay of gates and interconnects is affected by the supply voltag...
Ye Tao, Sung Kyu Lim
ICCAD
2009
IEEE
89views Hardware» more  ICCAD 2009»
13 years 5 months ago
Decoupling capacitance efficient placement for reducing transient power supply noise
Decoupling capacitance (decap) is an efficient way to reduce transient noise in on-chip power supply networks. However, excessive decap may cause more leakage power, chip resource...
Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. T...
MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
14 years 2 months ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...