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» Logic design for low-voltage low-power CMOS circuits
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DAC
2006
ACM
14 years 9 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang
DAC
2005
ACM
14 years 9 months ago
Designing logic circuits for probabilistic computation in the presence of noise
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
ENGL
2007
63views more  ENGL 2007»
13 years 8 months ago
A Full Integrated Gain Variable LNA for WCDMA
—In this paper we propose a gain-variable low noise amplifier (LNA) for low-voltage and low power WCDMA application. The LNA is designed based on a current-reused topology and a ...
Zhi-Ming Lin, Yu-Chun Huang
DAC
2006
ACM
14 years 9 months ago
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....
GLVLSI
2008
IEEE
190views VLSI» more  GLVLSI 2008»
14 years 3 months ago
A low leakage 9t sram cell for ultra-low power operation
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi