233 search results - page 8 / 47 » Logic design for low-voltage low-power CMOS circuits |
JOLPE
2010
13 years 7 months ago
2010
This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft e...
VLSID
2003
IEEE
14 years 9 months ago
2003
IEEE
This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data...
ASPDAC
1999
ACM
14 years 27 days ago
1999
ACM
-- This paper proposes an approach to reduce the short circuit current of CMOS off-chip drivers by individually controlling the input slew rates 10 the P and N channel transistors ...
ISVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper presents a two-stage CMOS differential voltage-controlled ring oscillator (VCO). The VCO is intended to operate as a frequency synthesizer in a PLL to generate local os...
ISLPED
2006
ACM
14 years 2 months ago
2006
ACM
In this paper, we identify the key challenges that oppose subthreshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges. Categorie...