1010 search results - page 46 / 202 » Logics for Contravariant Simulations |
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Reliability of logic circuits is emerging as an important concern that may limit the benefits of continued scaling of process technology and the emergence of future technology al...
ISMVL
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper we present fault tolerant CMOS logic using redundancy and ternary signals. The ternary gates are implemented using recharge logic which can be exploited in binary an...
APCCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...
PATMOS
2004
Springer
14 years 1 months ago
2004
Springer
Abstract. The logical effort method has appeared very convenient for fast estimation and optimization of single paths. However it necessitates a calibration of all the gates of the...
PDP
1997
IEEE
14 years 7 days ago
1997
IEEE
Event tracing and monitoring of parallel applications are difficult if each processor has its own unsynchronized clock. A survey is given on several strategies to generate a glob...