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EURODAC
1994
IEEE
211views VHDL» more  EURODAC 1994»
14 years 7 days ago
Advanced simulation and modeling techniques for hardware quality verification of digital systems
synchronisation also play a fundamental role in overall system robustness. ElectroMagnetic Compatibility (EMC) and ElectroMagnetic Interference (EMI) issues also have to be conside...
S. Forno, Stephen Rochel
ISPASS
2009
IEEE
14 years 2 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
DATE
2009
IEEE
168views Hardware» more  DATE 2009»
14 years 2 months ago
Selective state retention design using symbolic simulation
Abstract—Addressing both standby and active power is a major challenge in developing System-on-Chip designs for batterypowered products. Powering off sections of logic or memorie...
Ashish Darbari, Bashir M. Al-Hashimi, David Flynn,...
PACS
2004
Springer
115views Hardware» more  PACS 2004»
14 years 1 months ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...
ASPDAC
2010
ACM
165views Hardware» more  ASPDAC 2010»
13 years 6 months ago
Dynamic power estimation for deep submicron circuits with process variation
- Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow...
Quang Dinh, Deming Chen, Martin D. F. Wong