To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
William Jalby, Christophe Lemuet, Sid Ahmed Ali To...
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
This paper presents new achievements on the automatic mapping of algorithms, written in imperative software programming languages, to custom computing machines. The reconfigurable ...
— This paper presents a multiple-voltage high-level synthesis methodology for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by...
Reconfigurable Architectures are good candidates for application accelerators that cannot be set in stone at production time. FPGAs however, often suffer from the area and perfor...