1307 search results - page 101 / 262 » Low Power Hardware for a High Performance PDA |
164
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ISQED
2010
IEEE
15 years 8 months ago
2010
IEEE
- In a multi-core system, power and performance may be dynamically traded off by utilizing power management (PM). This paper addresses the problem of minimizing the total power con...
179
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ISLPED
2005
ACM
15 years 11 months ago
2005
ACM
Leakage power reduction in cache memories continues to be a critical area of research because of the promise of a significant pay-off. Various techniques have been developed so fa...
152
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ICCD
2004
IEEE
16 years 3 months ago
2004
IEEE
Network-on-chip (NoC) has been proposed as a solution for the communication challenges of System-on-chip (SoC) design in the nanoscale regime. SoC design offers the opportunity fo...
167
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VTS
2008
IEEE
16 years 15 days ago
2008
IEEE
— Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring thes...
160
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ISQED
2006
IEEE
16 years 4 days ago
2006
IEEE
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...