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» Low Power Hardware for a High Performance PDA
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DATE
2009
IEEE
248views Hardware» more  DATE 2009»
16 years 27 days ago
KAST: K-associative sector translation for NAND flash memory in real-time systems
Abstract—Flash memory is a good candidate for the storage device in real-time systems due to its non-fluctuating performance, low power consumption and high shock resistance. Ho...
Hyun-jin Cho, Dongkun Shin, Young Ik Eom
ASYNC
2002
IEEE
115views Hardware» more  ASYNC 2002»
15 years 11 months ago
Point to Point GALS Interconnect
Reliable, low-latency channel communication between independent clock domains may be achieved using a combination of clock pausing techniques, self-calibrating delay lines and an ...
George S. Taylor, Simon W. Moore, Robert D. Mullin...
DATE
2008
IEEE
182views Hardware» more  DATE 2008»
16 years 18 days ago
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
Swaroop Ghosh, Patrick Ndai, Kaushik Roy
DAC
2008
ACM
16 years 7 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...
137
Voted
ICCD
2002
IEEE
114views Hardware» more  ICCD 2002»
16 years 3 months ago
Balancing the Interconnect Topology for Arrays of Processors between Cost and Power
High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming...
Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Che...