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ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
15 years 11 months ago
Peak temperature control and leakage reduction during binding in high level synthesis
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
ISQED
2005
IEEE
162views Hardware» more  ISQED 2005»
15 years 11 months ago
Controlled-Load Limited Switch Dynamic Logic Circuit
Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primar...
Jayakumaran Sivagnaname, Hung C. Ngo, Kevin J. Now...
ERSA
2007
86views Hardware» more  ERSA 2007»
15 years 7 months ago
High-Precision BLAS on FPGA-enhanced Computers
The emergence of high-density reconfigurable hardware devices gives scientists and engineers an option to accelerating their numerical computing applications on low-cost but power...
Chuan He, Guan Qin, Richard E. Ewing, Wei Zhao
DAC
2004
ACM
16 years 7 months ago
FPGA power reduction using configurable dual-Vdd
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
Fei Li, Yan Lin, Lei He
ICS
2005
Tsinghua U.
15 years 11 months ago
Optimization of MPI collective communication on BlueGene/L systems
BlueGene/L is currently the world’s fastest supercomputer. It consists of a large number of low power dual-processor compute nodes interconnected by high speed torus and collect...
George Almási, Philip Heidelberger, Charles...